What is ECL in digital electronics

Circuit technology of digital circuits

C-MOS technology

Most integrated circuits of modern digital components use MOS field effect transistors instead of bipolar transistors. The metal-oxide-semiconductor FETs can be produced more easily in the chip and with greater packing density. The control takes place without current by changing the potential between the gate and source electrodes. The MOS technology is divided into the P-MOS, N-MOS and the well-known C-MOS subfamily. All use normally-off p- and n-channel MOS field effect transistors.

The designation C-MOS stands for complementary-metal-oxide-semiconductor. The circuit is constructed with self-locking, complementary MOS-FETs based on p- and n-channel technology. In the blocked state, MOS-FETs have such a high resistance that practically no quiescent current flows. There is also no control power as with bipolar transistors, since the gate is electrically separated from the substrate by a very thin quartz insulation. The control takes place without current by changing the electric field strength, the voltage at the gate-source path.

The extended voltage range of 3 ... 15 volts for C-MOS modules is an advantage. The normally used operating voltages are 3, 5, 10 and 15 volts. The high voltage range has a positive effect on the signal-to-noise ratio. A disadvantage is the risk of breakdown of the MOS transistors if the static charge is too high. Integrated Zener diodes ensure a small input protection.

In C-MOS circuits, all inputs must have a defined potential. Unused open inputs act like an antenna and absorb environmental potentials and create undefined output states. The circuits tend to oscillate in an uncontrolled manner. Since the junction capacitances are recharged at the moment of switchover by a small displacement current, the otherwise negligible power loss increases. In C-MOS technology, all pins, including those of the unused gates, must therefore be fully connected.

C-MOS inverter

The following figure shows the basic C-MOS circuit of a NOT gate or inverter. In the case of a normally-off n-channel MOS-FET, the drain-source path, the channel, becomes conductive when the gate-source voltage is positive. In the case of a normally-off p-channel MOS-FET, the drain-source path becomes conductive when the gate-source voltage is negative. In this inverter circuit, one transistor is always conductive and the other is blocked.

If the output level is 0 V or low, the p-channel MOS-FET blocks. At an output level of 5 V or high, the n-channel MOS-FET is blocked. In both cases there is no current. The power conversion in C-MOS elements is very low and only occurs in the brief moment of switching when the small transistor capacitances are recharged. It depends on the switching frequency.

C-MOS NAND and NOR gates

The following figure shows two basic C-MOS circuits for one NOR and NAND gate with two inputs. The substrate or bulk electrodes are connected in such a way that they are connected to the operating voltage for the p-channel transistor and to ground for the n-channel transistor. The channel is controlled via the gate-source potential and, for the middle transistors, correspondingly via the gate-bulk potential.

The output of the NOR gate only has a high level when the transistors K1 and K2 are conducting and K3 and K4 are blocked at the same time. This case occurs when both inputs have a low level. When A = H, K1 blocks and disconnects output Y from the operating voltage. Even if K2 were to conduct because B = L, there is no connection to the operating voltage because of the blocked transistor K1. With A = H or B = H, either K3 or K4 is conductive. Both times the output is switched to ground with low resistance and Y = L.

The switching behavior for the NAND is derived accordingly. Only with A = H and B = H are transistors K1 and K2 blocked and the output is separated from the operating voltage. At the same time, K3 and K4 conduct and switch the output to ground. If one of the inputs has a high level, the output is connected to the operating voltage with low resistance, since K1 and K2 are connected in parallel. One of the two n-channel MOS-FETs connected in series blocks the connection to ground and Y = H remains at the output.

The level diagrams, which can be determined from the transfer characteristics, show optimal values ​​with greater signal-to-noise ratios compared to the TTL elements. The figure shows the voltage ranges for high and low levels for two operating voltages.

For a high level at the output, the value in C-MOS technology may be H = ≥ 0.9 · Ucc. The low level at the output is in the range L = ≤ 0.1 · Ucc. The values ​​H = ≥ 0.66 · Ucc and L = ≤ 0.33 · Ucc apply to the input.

Since the output and input currents are negligibly small at less than 0.1 µA, output load factors greater than 50 result. Many more circuits can be operated in a network. The signal propagation times in the normal C-MOS series are 40 ns ... 90 ns. In a further development, the metal gates were replaced by silicon gates, which leads to high-speed C-MOS technology. The signal propagation time of the HCMOS elements is comparable to that of the TTL elements. With the designation 74HCxxx, they are usually pin compatible with the 74LSxxx-TTL circuits. They are controlled with the typical C-MOS input levels and are designed for operating voltages between 2 V and 6 V.

C-MOS transmission link

If an n-channel and p-channel C-MOS transistor are connected in parallel and controlled with inverse logic levels, then the circuit behaves like a switch. An analog or digital signal can be bidirectionally allowed to pass through with low resistance or blocked with high resistance between the input and output. The circuit, which is comparable to a mechanical switch, works wear-free, bounce-free and even at very high switching frequencies. The disadvantage of the standard circuit is the higher forward resistance of 300 Ω to 1.5 kΩ. With circuit expansions, the value could be reduced to typically 150 Ω.

With G1 = +5 V and G2 = 0 V, both MOS transistors are blocked with 0 V control voltage between the gate substrate (bulk). The line between X and Y is high-resistance, the switch is open.
With G1 = 0 V, the gate-bulk control voltage becomes −5 V and the p-channel MOS transistor becomes conductive. With G2 = +5 V, the gate-bulk control voltage becomes +5 V and the n-channel MOS transistors are conductive. The path between X and Y is low-resistance, the switch is closed.

For error-free switching, the analog or digital signals to be switched at the equivalent input and output must be within the operating voltage. In analog operation, operating voltages between ± 5 V symmetrical to ground are advantageous. For this purpose, C-MOS analog switches with internal level conversion were developed, which are still controlled with normal digital levels 0 V low and +5 V high. The transmission element is controlled digitally with a C-MOS inverter.

This basic circuit simplifies many highly integrated digital circuits that can work, for example, bidirectionally like multiplexers and demultiplexers. They are integrated in clocked and feedback circuits such as flip-flops, registers and memory modules.